As technology nodes shrink, in some integrated circuit designs there has been a desire to eliminate use of polysilicon gate electrodes to improve device performance with decreased feature sizes. Replacing polysilicon gate structures with metal gate structures is one solution. Replacement metal gate structures can provide superior Tinv (inversion layer thickness)−Vt (threshold voltage) performance. However, in conventional fabrication methods it is difficult to control replacement metal gate structure heights. Specifically, multiple spacer etching and source/drain pre epi clean processes result in thickness variation for the hardmasks covering temporary polysilicon gate electrodes. Conventionally, these hardmasks are used as stops for planarization processes during replacement metal gate preparation. Therefore, variability in hardmask thickness leads to variability in replacement metal gate structure height. It is desirable to eliminate variability in replacement metal gate structure height to improve device performance.
Further, as gate pitches decrease, the parasitic capacitance component between gates and contact plugs becomes increasingly significant. Therefore, it is desirable to implement a lower K dielectric between the gates and contacts to reduce capacitance.
Accordingly, it is desirable to provide semiconductor devices having metal gate structures with a uniform height and methods for fabricating semiconductor devices having metal gate structures with a uniform height. In addition, it is desirable to provide semiconductor devices and methods for fabricating semiconductor devices with reduced parasitic capacitance. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.